Course Description
The i.MX51 is a 4-day class lecture covering the main features of the i.MX51 architecture, operation and programming.
This course covers the ARM Cortex A8™ platform including programming model exceptions and interrupt handling, interrupt controller, instruction set, Application Processor level 1 and level 2 caches, cross-bar switch, Memory Management Unit (MMU), application processor I/O peripherals, Smart Direct Memory, Access Control, Multi-master Multi-Memory Interfaces (M4IF), Graphics and Image Processing unit (IPU) and system wide integration.
Target Applications: Wireless device running computationally intensive multimedia applications such as portable media players and portable navigation devices. Target devices also include feature rich smart phones, digital video recorders, digital cameras, mobile gaming consoles, mobile multimedia players and many other mobile wireless applications.
Prerequisites
Due to the high degree of functionality and integration of this device, the student is encouraged to gain some familiarity beforehand by reviewing current Freescale documentation for this product. Introductory level web-based training materials are available at www.freescale.com/training. Search on i.MX51 for a list of available overview materials.
Target Group
Application Software and system engineers who need to come up to speed quickly on how to design with this architecture.